As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, the storage capacity of memory devices has continued to increase at geometric proportions. This increased capacity, coupled with the geometrically higher operating speeds of electronic systems containing memory devices, has made high memory device bandwidth ever more critical. One application in which memory devices, such as dynamic random access memory (“DRAM”) devices, require a higher bandwidth is their use as system memory in computer systems. As the operating speed of processors has increased, processors are able to read and write data at correspondingly higher speeds. Yet conventional DRAM devices often do not have the bandwidth to read and write data at these higher speeds, thereby slowing the performance of conventional computer systems. This problem is exacerbated by the trend toward multi-core processors and multiple processor computer systems. It is currently estimated that computer systems operating as high-end servers are idle as many as 3 out of every 4 clock cycles because of the limited data bandwidth of system memory devices. In fact, the limited bandwidth of DRAM devices operating as system memory can reduce the performance of computer systems to as low as 10% of the performance of which they would otherwise be capable.
Various attempts have been made to increase the data bandwidth of memory devices. For example, wider internal data buses have been used to transfer data to and from arrays with a higher bandwidth. However, doing so usually requires that write data be serialized and read data deserialized at the memory device interface. Another approach has been to simply scale up the size of memory devices or conversely shrink their feature sizes, but, for a variety of reasons, scaling has been incapable of keeping up with the geometric increase in the demand for higher data bandwidths. Proposals have also been made to stack several integrated circuit memory device dice in the same package.
Several other issues often arise in the design and use of memory devices. One of these issues is power consumption. In some applications, such as in portable electronic devices, power consumption is very important because it can seriously reduce the operating time of battery powered devices such as laptop computers. Minimizing power consumption is important even for electronic devices that are not battery powered because reducing power reduces the heat generated by the memory devices.
Another issue that often arises is the inadvertent loss of data stored in memory devices, such as dynamic random access memory (“DRAM”) devices. DRAM devices need to be periodically refreshed to avoid loosing data. If DRAM devices are not refreshed frequently enough, data retention errors can occur. Unfortunately, refresh consumes a substantial amount of power, thus making it desirable to minimize the frequency of refreshes. As a result of this trade-off between power consumption and minimizing data errors, DRAM devices are often refreshed near the rate at which data retention errors can occur. Data retention errors can also occur in other types of memory devices, such as flash memory devices, for different reasons. The time duration before which data retention errors become an issue can be extended by generating an error correcting code (“ECC”) for each item of write data, and storing the ECC in the memory device with the write data. When the data are read, the ECC is read along with the read data and used to determine if a data retention error has occurred, and, if so, the ECC can often be used to correct the error.
Still another issue that often arises in the design of memory devices is minimizing the signal connections to the die of the memory device. The area used by bond wire consumes space on the die that could be used for fabricating transistors to increase the capacity of the memory device. The same problem also exists for the area consumed on a memory device die by through silicon vias (“TSVs”) connected to stacked memory devices.
As mentioned above, proposals have been made to increase the bandwidth of a memory device by stacking several integrated circuit memory device dice in the same package. Although doing so does to some extent alleviate the problem of limited bandwidth, it can exacerbate the other problems discussed above, including power consumption and consuming excessive die area with TSVs, particularly if ECC techniques are to be used to correct data retention errors.
Therefore, a need exists for a method and system to stack memory device dice in a manner that maximizes the area of a die available for memory capacity, does not unduly increase the number of required terminals, and does not substantially increase power consumption.